Die shot

¶ MIPS: an R2000 implementation

The title of this page is the name of the paper I co-authored, which describes a project I was part of in 2007 where 34 undergrads spent a semester developing a MIPS implementation starting at the ISA, all the way down to verification, fabrication and bringup.

¶ Blog post

I wrote this blog post in February 2008, but never got around to publishing it

Last year I was part of a team of four at my uni, the University of Adelaide, who collaborated with a team of 30 students at Harvey Mudd College in Claremont, California. We were to design and implement a CPU beginning with the Instruction Set Architecture, through to layout, fabrication, verification, and performance testing.

Seven of the original 34 students, along with our supervisors David Money Harris from HMC, and Braden Phillips from UoA, submitted a paper titled A MIPS R2000 Implementation to the 45th DAC/ISSCC Student Design Contest. In February 2008, we were informed this month that our paper was selected as a winner.

I gave a lightning talk about the chip at the Embedded Miniconf at Linux.conf.au 2008.

What follows is a description of the project, and our chip. It is aimed at those with a small amount of microelectronics knowledge.

The first MIPS processor entered the market in 1985, and since then variations of the architecture have been used in the Sony PlayStation Portable and Nintendo 64, and many other embedded applications. The first R2000 chip ran at 8Mhz, on a 2-micron process, containing thirty-two 32-byte registers, and a 5 stage pipeline. Our chip was to follow the same design where possible.

Our microarchitecture was designed in Verilog, which gave us a runnable top level design to follow, and this was used as a reference in the design of schematics. These schematics were then laid out by hand using GNU Electric. Unlike the original R2000, our design has an on-chip 512 byte instruction, 512 byte data, write-through, directly mapped cache. There is also a signed radix-4 Booth multiply/divide unit, that is capable of executing muti/div instructions while not stalling executing of other operations.

The final design was fabricated by MOSIS, on an AMI 0.5-micron process. It contained 160,000 transistors, and executed code correctly at 7.25Mhz.

As part of the project, we designed our own standard cell library. It contains 257 cell, and along with all the material used in designing the chip as well as the chip design itself, is available under the MIT licence. We also used a GCC toolchain to compile c programs for the testbed platform, which consists of our MIPS CPU, a custom PCB containing a socket and LCD display, and memory subsystem implemented on a FPGA. All of this was completed in a semester.